Delay Estimation for On-Chip VLSI Interconnect using Weibull Distribution Function

Abstract

In deep sub-micrometer (DSM) regime the on-chip interconnect delay is significantly more dominating than the gate delay. Several approaches have been proposed to capture the interconnect delay accurately and efficiently. By interpreting the impulse response of a linear circuit as a probability distribution function (PDF), Elmore first estimated the interconnect delay. Several other approaches like PRIMO, AWE, h-Gamma, WED, D2M etc. have been reported so far, which are shown to be more accurate delay estimation compared to Elmore delay metric. But they suffer from computational complexity when using in the total IC design processes. Our work presents a closed form formula for interconnect delay. The delay metric is derived by matching circuit moments to the Weibull distribution. The delay metric can be easily implemented for both step and ramp inputs by using a single look-up table. Experiments validate the effectiveness of the delay metric for nets from a real industrial design.