Modified Nine Level Multi Level Inverter Topology for Trinary Sequences with Reduced Switches and Switching Losses

H. S. Chaithra, C. B. Shankaralingappa
{"title":"Modified Nine Level Multi Level Inverter Topology for Trinary Sequences with Reduced Switches and Switching Losses","authors":"H. S. Chaithra, C. B. Shankaralingappa","doi":"10.1109/RTEICT52294.2021.9573773","DOIUrl":null,"url":null,"abstract":"This paper presents a newly modified nine level multilevel inverter (MLI) topology. This MLI uses reverse voltage circuit concept and the input dc sources employs trinary asymmetric sequence. It provides highest output voltage level with minimum dc supply and electrical switch count in comparison to alternative sequences. Utilizing of trinary sequence MLI generates all additive and subtractive combinations of input dc voltages at the output. This topology is implemented on 9-level asymmetric MLI using less number of active and passive elements. Unipolar pulse width modulation technique is employed to generate gating pulses. The proposed topology is simulated in MATLAB/Simulink and efficiency, THD, power losses are determined. Results indicate better performance, i.e., lesser losses, minimal switches, and cost with acceptable THD.","PeriodicalId":191410,"journal":{"name":"2021 International Conference on Recent Trends on Electronics, Information, Communication & Technology (RTEICT)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2021-08-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 International Conference on Recent Trends on Electronics, Information, Communication & Technology (RTEICT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/RTEICT52294.2021.9573773","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0

Abstract

This paper presents a newly modified nine level multilevel inverter (MLI) topology. This MLI uses reverse voltage circuit concept and the input dc sources employs trinary asymmetric sequence. It provides highest output voltage level with minimum dc supply and electrical switch count in comparison to alternative sequences. Utilizing of trinary sequence MLI generates all additive and subtractive combinations of input dc voltages at the output. This topology is implemented on 9-level asymmetric MLI using less number of active and passive elements. Unipolar pulse width modulation technique is employed to generate gating pulses. The proposed topology is simulated in MATLAB/Simulink and efficiency, THD, power losses are determined. Results indicate better performance, i.e., lesser losses, minimal switches, and cost with acceptable THD.
减少开关和开关损耗的改进九电平多电平逆变器拓扑结构
提出了一种改进的九电平多电平逆变器拓扑结构。该MLI采用反向电压电路概念,输入直流电源采用三元非对称序列。与替代序列相比,它提供最高的输出电压水平,最小的直流电源和电气开关计数。利用三阶序列,MLI在输出端产生输入直流电压的加和减组合。这种拓扑结构是在使用较少数量的有源和无源元素的9级非对称MLI上实现的。采用单极脉宽调制技术产生门控脉冲。在MATLAB/Simulink中对所提出的拓扑进行了仿真,并确定了效率、THD和功耗。结果表明性能更好,即损耗更小,开关最小,THD成本可接受。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 求助全文
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:604180095
Book学术官方微信