Explorations of sequential ATPG using Boolean satisfiability

Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium Pub Date : 1993-04-06 DOI:10.1109/VTEST.1993.313303

H. Konuk, T. Larrabee

引用次数: 34

Abstract

Presents a sequential test generation method based on Boolean satisfiability. The method produces near-minimal test sizes. The authors discuss the flexibility provided by Boolean satisfiability to extend the fault model to realistic faults. Experimental results using ISCAS-89 benchmark circuits and comparisons with previously published results are presented.<>

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利用布尔可满足性探索序列ATPG

提出了一种基于布尔可满足性的顺序测试生成方法。该方法产生的测试尺寸接近最小。作者讨论了布尔可满足性所提供的将故障模型扩展到实际故障的灵活性。本文给出了ISCAS-89基准电路的实验结果，并与先前发表的结果进行了比较。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium

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