A highly efficient UHF RFID frontend approach

Abstract

The passive radio frequency identification (RFID) presents a key technology for unattended wireless networks. To achieve a higher reading range and to improve the operational reliability of passive RFID tags, the design of integrated circuits with an ultra low power consumption and novel concepts for high-efficiency energy harvesting are required. This paper presents a highly efficient analog frontend for passive UHF RFID transponders. This frontend includes a multistage Schottky rectifier, a backscatter modulator, an ASK demodulator, a current reference source, and power limiting circuits. These building blocks are implemented in a 0.14 µm CMOS technology. The measured overall RF-to-DC conversion efficiency of the analog frontend for a DC output power of 10 µW (1V and 10 µA) is about 20%. The DC power consumption of the analog building blocks is about 1 µW for a supply voltage of 1V.