Memristor-Based Neuromorphic Hybrid CMOS Sub-Block Architecture for a High-Speed Arithmetic and Logic Unit

Abstract

Presently, Computations traverse through several layers of hardware logic structures to perform the intended operation. This, amounts to a significant time delay and power consumption. In this paper, a memristor-based ALU architecture is proposed which is a combination of trained Memristor-based Neural Networks and hybrid CMOS circuits which together can form a promising solution to Implement High-Speed Logic. We will discuss a Neural Network to implement an N-Bit Full Adder. Further, an N-Bit Hybrid CMOS Fast Multiplier architecture is proposed; which uses an N-Bit Full Adder Neural Network as well as Memristor-based Hybrid CMOS Logic Circuits to implement the entire Functionality. Also a 2-Bit Neural full adder is trained using Back Propagation algorithm which gives a better insight into the Robustness of the architecture. The comparison analysis of the CMOS as well as the proposed Memristor-based Neural 2-Bit Full adder is shown. Systems which use repetitive logic computations; for instance, DSP processors can benefit highly from the proposed architecture by simply cutting down on the Time and Power spent on Complex Real-Time Calculations (matrix DFT-FFT computations).