The Design of a Cycle Accurate Multi-core Architecture Performance Simulator

Abstract

As multi-core technology has become the trend to improve the performance of processor, there is more need to design a performance simulator for the design of multi-core architecture and for the evaluation of system performance. However there are few simulators that support different architectures of multi-core processor well. This paper presents a design and implementation of a cycle accurate multi-core processor architecture simulator, it is a component design, which can be customized to different multi-core architectures, furthermore, provides a practical tool for the design and evaluation of multi-core architecture.