The Guiding Light for Chip Testing

Abstract

Scaling of transistor feature size over time has been facilitated by corresponding improvement in lithography technology. However, in recent times the wavelength of the optical light source used for photolithography has not scaled. Starting with 180nm devices, the wavelength of optical source has remained the same at 193nm. Consequently, current and upcoming technology nodes at 65nm, 45nm, 32nm and 22nm will be using a light source with wavelength much greater than the feature size. This creates a peculiar problem where line width on manufactured devices is a function of relative spacing between adjacent lines. Despite numerous restriction on layout rules, interconnects may still suffer from constriction due to this peculiarity also known as forbidden pitch problem. In this talk, we will explore the range of issues that arise from photolithography as they relate to chip testing.