FPGA implementation of relay-type correlator for noise radar applications

Abstract

A new implementation of multiplier-less relay correlator in FPGA has been suggested and tested. The novel approach suggested enables exclusion of multipliers usage that saves FPGA resources and, hence, increases number of parallel channels in digital time integrating correlator, which, in particular, speed up target range & velocity estimation and extends Noise Radar working range. All this provides a good basis for design of a software defined Noise Radar with digital generation of radar signals and coherent processing of radar returns in real-time mode.