{"title":"Temperature effects on an HfO2-TiO2-HfO2 stack layer resistive random access memory cell for low power applications","authors":"N. A, N. M. Sivamangai, R. Naveenkumar","doi":"10.1109/ICDCS48716.2020.243597","DOIUrl":null,"url":null,"abstract":"In this paper we analyzed the forming voltage (Vf) and resistive switching characteristics of the fabricated nano structured trilayer resistive switching device (Pt/HfO2/TiO2/HfO2/Pt). Standard fabrication process is opted with a post metal annealing (PMA) process to diminish the forming voltages of stack layer resistive random access memory (RRAM) cells. Result reveals after the post metal annealing, the Vf is reduced to 3.6 V from 4.4 V at room temperature (25°C). In addition at high background temperature (80°C) the Vf value is diminished significantly (3.2 V) compared to lower temperatures, 50° C and 25° C. We optimized, the forming environment temperature (80° C), compliance current (30 µA) for the further reduction of Vf value.","PeriodicalId":307218,"journal":{"name":"2020 5th International Conference on Devices, Circuits and Systems (ICDCS)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 5th International Conference on Devices, Circuits and Systems (ICDCS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICDCS48716.2020.243597","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
In this paper we analyzed the forming voltage (Vf) and resistive switching characteristics of the fabricated nano structured trilayer resistive switching device (Pt/HfO2/TiO2/HfO2/Pt). Standard fabrication process is opted with a post metal annealing (PMA) process to diminish the forming voltages of stack layer resistive random access memory (RRAM) cells. Result reveals after the post metal annealing, the Vf is reduced to 3.6 V from 4.4 V at room temperature (25°C). In addition at high background temperature (80°C) the Vf value is diminished significantly (3.2 V) compared to lower temperatures, 50° C and 25° C. We optimized, the forming environment temperature (80° C), compliance current (30 µA) for the further reduction of Vf value.