Program interference in MLC NAND flash memory: Characterization, modeling, and mitigation

Yu Cai, O. Mutlu, E. Haratsch, K. Mai
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引用次数: 196

Abstract

As NAND flash memory continues to scale down to smaller process technology nodes, its reliability and endurance are degrading. One important source of reduced reliability is the phenomenon of program interference: when a flash cell is programmed to a value, the programming operation affects the threshold voltage of not only that cell, but also the other cells surrounding it. This interference potentially causes a surrounding cell to move to a logical state (i.e., a threshold voltage range) that is different from its original state, leading to an error when the cell is read. Understanding, characterizing, and modeling of program interference, i.e., how much the threshold voltage of a cell shifts when another cell is programmed, can enable the design of mechanisms that can effectively and efficiently predict and/or tolerate such errors. In this paper, we provide the first experimental characterization of and a realistic model for program interference in modern MLC NAND flash memory. To this end, we utilize the read-retry mechanism present in some state-of-the-art 2Y-nm (i.e., 20-24nm) flash chips to measure the changes in threshold voltage distributions of cells when a particular cell is programmed. Our results show that the amount of program interference received by a cell depends on 1) the location of the programmed cells, 2) the order in which cells are programmed, and 3) the data values of the cell that is being programmed as well as the cells surrounding it. Based on our experimental characterization, we develop a new model that predicts the amount of program interference as a function of threshold voltage values and changes in neighboring cells. We devise and evaluate one application of this model that adjusts the read reference voltage to the predicted threshold voltage distribution with the goal of minimizing erroneous reads. Our analysis shows that this new technique can reduce the raw flash bit error rate by 64% and thereby improve flash lifetime by 30%. We hope that the understanding and models developed in this paper lead to other error tolerance mechanisms for future flash memories.
MLC NAND闪存中的程序干扰:表征、建模和缓解
随着NAND闪存继续缩小到更小的工艺技术节点,其可靠性和耐用性正在下降。可靠性降低的一个重要原因是程序干扰现象:当一个闪存单元被编程为一个值时,编程操作不仅影响该单元的阈值电压,还影响周围其他单元的阈值电压。这种干扰可能会导致周围的单元移动到与其原始状态不同的逻辑状态(即阈值电压范围),从而导致读取单元时出现错误。对程序干扰的理解、表征和建模,即当另一个细胞被编程时,一个细胞的阈值电压会发生多大的变化,可以使设计的机制能够有效地预测和/或容忍这种错误。在本文中,我们提供了现代MLC NAND闪存中程序干扰的第一个实验表征和现实模型。为此,我们利用一些最先进的2Y-nm(即20-24nm)闪存芯片中存在的读取重试机制来测量特定单元被编程时单元阈值电压分布的变化。我们的结果表明,一个细胞接收到的程序干扰的数量取决于1)被编程细胞的位置,2)细胞被编程的顺序,以及3)被编程细胞及其周围细胞的数据值。基于我们的实验表征,我们开发了一个新的模型,预测程序干扰量作为阈值电压值和相邻细胞变化的函数。我们设计并评估了该模型的一个应用,该模型将读取参考电压调整为预测的阈值电压分布,目标是最大限度地减少错误读取。我们的分析表明,这种新技术可以将原始闪存误码率降低64%,从而将闪存寿命提高30%。我们希望本文中开发的理解和模型能够为未来的闪存带来其他容错机制。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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