Constant coefficient multiplication in FPGA structures

Abstract

Investigates different architectures implementing bit-parallel constant-coefficient multiplication in FPGA structures. First, multiplierless multiplication (MM) architectures employing canonic sign digit (CSD) and sub-structure sharing methods are addressed, and a novel algorithm for the conversion from two's-complement to CSD representation is presented. In the second part of this paper, lookup table-based multiplication (LM) is investigated. Correspondingly, the usage of different memory modules and finding the optimal combination of the memory and adders are considered. The LM architecture also considers reduction of the address width for each memory cell and the possibility of memory sub-structure sharing. Finally, implementation results for the Xilinx XC4000 and Virtex families are presented. As a result, MM generally surpasses the LM architecture. However, the actual choice between these two architectures is coefficient- and input parameter-dependent.