Scalable architectures for high speed channel decoding

Abstract

At present, channel decoding and soft output channel decoding of convolutional codes are key technologies for advanced communication systems. The speed of any implementation of the corresponding decoding algorithms, the Viterbi algorithm (VA) and the soft output VA (SOVA) is limited by an inherent nonlinear recursion. In contrast this paper deals with scalable architectures for purely feedforward decoding algorithms, the "minimized method" parallelized Viterbi decoding algorithm and the parallel MAP (Maximum A Posteriori) soft output decoding algorithm. A unified treatment is possible since these algorithms and the corresponding dependence graphs (DGs) are very similar. In order to obtain a scalable throughput adapted to a given specification, a hierarchical resource sharing methodology exploiting the inherent DG regularity is proposed and implemented as a VHDL generator.