A 2.5GHz, 30mW, 0.03mm2, All-Digital Delay-Locked Loop

Abstract

A. 2.5GHz, 30mW, 0.03mm2, all-digital DLL in 0.13mum CMOS technology is presented. The lattice delay unit provides both a small delay step and a fixed intrinsic delay of two NAND gates. A modified binary search controller reduces the locking time and allows the DLL to track the PVT variations. This DLL locks in 24 cycles and has the closed-loop characteristic with pk-pk jitter of 14ps.