A Novel Biphasic Neuron Encoder Implementation

Abstract

In an effort to address the issue of low power and area constraints which are important pre-requisites to many applications in the field of signal processing, this work focuses on the implementation of a novel biphasic neuron architecture, that is proven to be energy efficient, and highly compact. The low power Adaptive exponential integrate and fire neuron (ADEx I&F), is implemented as a biphasic encoder in 180 nm CMOS Technology, and a SER of upto 60 dB and a figure of merit (FOM) of 0.26 pJ/conversion is achieved. The proposed biphasic encoder is found to exhibit similar performance characteristics with respect to the existing architectures while comprising of 52 % lesser number of transistors than the conventional biphasic neuron encoder models.