{"title":"A profile driven approach for low power synthesis","authors":"S. Katkoori, Nand Kumar, L. Rader, R. Vemuri","doi":"10.1109/ASPDAC.1995.486399","DOIUrl":null,"url":null,"abstract":"A profile driven approach to behavioral synthesis is presented. For a given design and a set of input vectors, the switching activity in the design yields a measure of the power consumption. Every module in a parameterized module library is characterized by its average switching activity per input vector. For a given behavioral specification, simulation using user specified inputs is carried out to collect the profile data of various operations and carriers in the specification. In the performance estimation phase, the profile data with the switching activity data in the precharacterized module library is used to estimate the average switching activity of all the module sets meeting other user specified constraints such as area and delay. The module set with the least estimated switching activity is further synthesized. Experimental results show that the switching activity estimated during synthesis deviates by less than 10% on the average from the actual switching activity measured after completing synthesis.","PeriodicalId":119232,"journal":{"name":"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair","volume":"83 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1995-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASPDAC.1995.486399","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
Abstract
A profile driven approach to behavioral synthesis is presented. For a given design and a set of input vectors, the switching activity in the design yields a measure of the power consumption. Every module in a parameterized module library is characterized by its average switching activity per input vector. For a given behavioral specification, simulation using user specified inputs is carried out to collect the profile data of various operations and carriers in the specification. In the performance estimation phase, the profile data with the switching activity data in the precharacterized module library is used to estimate the average switching activity of all the module sets meeting other user specified constraints such as area and delay. The module set with the least estimated switching activity is further synthesized. Experimental results show that the switching activity estimated during synthesis deviates by less than 10% on the average from the actual switching activity measured after completing synthesis.