Cost optimum embedded DRAM design by yield analysis

Abstract

We study on cost optimum embedded DRAM interconnect technologies by using a simple VLSI particle-induced fault simulator modified for the embedded DRAM macro. The fault simulator is applied to an assumed 4-Mbit DRAM macro production process with DRAM interconnect technologies of DRAM 1/2 pitch 115 nm and ASIC 1/2 pitch of from 115 nm to 500 nm (peripheral circuits). The DRAM macro is included in a SoC chip that has area of 1 cm/sup 2/ and is manufactured on the wafer with size of 8 inches. Result shows that the wider pitch decreases the count of manufactured chips but increases the yield. ASIC 1/2 pitch of 0.4 /spl mu/m achieved maximum count of good chips per wafer under the assumed conditions. There exists the cost optimum embedded DRAM design.