Vedic Multiplier and Wallace Tree Adders Based Optimised Processing Element Unit for CNN on FPGA

Abstract

Convolutional Neural Networks (CNNs) have been effectively used for a variety of tasks, comprising image classification, detection and speech processing. CNNs possess computationally demanding methods and currently necessitates specialised hardware. Thus, hardware optimization for effective CNN accelerator design continues to be a difficult task. Most of the intensive computation on a CNN accelerator design is carried out by the processing element (PE). This article offers a novel processing element design based on Vedic multipliers and Wallace Tree adders as a substitute for hardware implementation. The proposed design achieves significant savings in hardware resources and power. The proposed Vedic multiplier results in minimum delay.