A SystemC AMS model of an 12C bus controller

Abstract

The authors present the design of an intellectual property (IP) modeling the interface controller for an inter-integrated controller channel (I2C) bus. AMS IPs such as bus interfaces, whose behaviour follows the bus protocols in terms of packet structure, timing constraints or control modes can offer solutions for the issue of communications between a system on a chip and its external environment. The model of our controller is written in SystemC in association with a SystemC-AMS description of the analog block. Simulation results are presented