Bandwidth reduced H.264/AVC hardware design with various windows of lossless compressor and cache scheme

Abstract

The bus bandwidth insufficiency and the real-time processing of H.264/AVC are the most serious problems in High Definition(HD) or Ultra Definition(UD) video data. This paper presents the bandwidth reduced architecture to solve these problems. By using various windows of lossless compressor and cache scheme with each controller, we can significantly reduce both data bandwidth and processing cycles.