Multiple-mode floating-point multiply-add fused unit for trading accuracy with power consumption

Abstract

With the wide use of floating-point (FP) multiply and accumulate operations in multimedia and digital signal processing applications, many modern processors adopt FP multiply-add fused unit (MAF) to achieve high performance, improve accuracy and reduce power consumption. However, FP arithmetic units usually occupy the major portion of a processor's area and power dissipation. In this paper, we will propose a multiple-mode FP multiply-add fused unit which utilizes the iterative multiplication and truncated addition techniques to support seven operating modes with various errors for low power applications. It can execute either one multiply-accumulate operation with three modes, one multiplication operation with two modes or one addition operation with two modes. When compared to the traditional IEEE754 single-precision FP MAF, the proposed unit has 4.5% less area and 23% longer delay to achieve multiple modes which can sacrifice a little (<; 1%) accuracy for saving large (> 33%) power consumption.