A fully automated large-scale addressable test chip design with high reliability

Abstract

During the development of modern semiconductor processes, which has increasing complexity and an extremely high number of degrees of freedom, a large number of distinct test structures are required to test and ensure the yield and manufacturability. To increase the utilization of chip area, addressable methodology of test chip is developed. In this paper, we present a novel large-scale addressable test chip development procedure. Based on components for automation, this procedure is fully integrated and able to reduce layout time to 10% and eliminate much of the potential for human error. A 32×32 array on a 45nm technology has been designed and manufactured with this procedure; the silicon test data further prove the reliability and effectiveness of this procedure.