Design of Heterogeneous Adders Based on Power-Delay Tradeoffs

Abstract

The performance of arithmetic adders varies widely in their power consumption, delay, and area requirements. To acquire more fine-grained tradeoffs in the power-delay tradeoff curve of a binary adder, the heterogeneous adder architecture is adopted. In heterogeneous adder architecture, a binary adder is decomposed into sub-adder blocks with different carry propagation schemes and precisions. Thus the method allows us to expand the original design space of a specific type of adder into the more fine-grained design space by mixing that of each sub-adder. In this paper, a design for heterogeneous adder through power optimization under delay constraints or delay optimization under power constraints was presented by determining the bitwidth of each sub-adder.