Modeling and Analysis a of On-Die Decoupling Capacitance in the Power Delivery Network of an Integrated Chip

S. Moon, Seonha Lee
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引用次数: 1

Abstract

In this work, we propose an analytical approach for accurate estimation on on-die decoupling capacitance in the power delivery network (PDN) of an integrated chip (IC). This paper suggests a simplified model of PDN which avoids the complex mesh structures traditionally generated but still provides a good fit model with measurement. The suggested model consists of branched multiple cells in a chained node formation. By manipulating multiple variables accounting for a complex PDN structure, the curve fitting process was performed and the best-fitted curve was found to be valid with less than 3% error tolerance through the solution-search processes by comparing capacitor values in a known mesh structure. Consequently, complex matrix PDN can be simplified and converted to an analytical model through the proposed chained structure. This approach is expected to effectively validate the value of implemented decoupling capacitance in the PDN of a designed IC with conventional low-impedance measurement techniques.
集成芯片供电网络中片内去耦电容的建模与分析
在这项工作中,我们提出了一种准确估计集成芯片(IC)供电网络(PDN)中片上去耦电容的分析方法。本文提出了一种简化的PDN模型,避免了传统生成的复杂网格结构,但仍然提供了与测量的良好拟合模型。所建议的模型由链式节点结构中的分支多个细胞组成。通过控制复杂PDN结构的多个变量,进行曲线拟合过程,通过比较已知网格结构中的电容值进行解搜索,发现最佳拟合曲线有效,误差小于3%。因此,通过所提出的链式结构,可以将复矩阵PDN简化并转换为解析模型。该方法有望通过传统的低阻抗测量技术有效地验证设计IC的PDN中实现的去耦电容的值。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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