EFT Transient Noise Model and Protection Analysis from Chip to System Level on Power Distribution

Abstract

This paper describes the utilization of ANSYS Designer with measurement validation to provide tool for analyzing, predicting and optimizing the EFT Burst transient noise suppression implementation and effectiveness to meet the requirement of IEC61000-4-4 [1] (EFT/B). In addition, the paper describes how electromagnetic simulations can provide chip-level immunity analysis for IEC 62215-3 [2]. The analysis of residual transient noise energy from transient noise suppressing devices can also provide significant benefits to EMS protection from chip, module, and all the way to board and system level. This study intends to provide an efficient simulation model to help electronic engineers enhancing their product design reliability.