Effect of Device Scaling on Lateral Migration Mechanism of Electrons in V-NAND

Abstract

In this paper, we analyzed lateral migration (LM) mechanism of V-NAND occurring during retention operation depending on scaling of geometric parameters using TCAD simulation. Modeling for LM was performed and the behavior of time-constant (τ) parameter used for modeling was analyzed. In addition, we analyzed retention characteristics according to the states of neighbor word line (WLNei.). Comparing the extracted τ for different patterns, checker-board pattern (C/P) has the smallest τ, followed by NPN and solid pattern (S/P).