Architecture of a CMOS fuzzy logic controller with optimized memory organisation and operator design

Abstract

A fuzzy logic control (FLC) unit as an on-chip part of a multi-purpose controller device is described. The architecture of the FLC is presented. The focus is on a method to implement the rule memory in a minimal memory space. A systematic analysis of the implementation of fuzzy MIN- or MAX-operators in digital CMOS circuits is included. A solution with minimal transistor count and maximal speed was found.<>