Finite-element modelling of stress induced wafer warpage for a full BiCMOS process

Abstract

A finite element method (FEM) wafer scale model considering all the process details, e.g. metal patterning, via etching, etc., is built for a state-of-the-art $0.13-\mu m$ SiGe BiCMOS fully processed 8-inch wafer. Associated layer residual stress and wafer warpage are extracted and compared with hand calculation and experimental results. The comparison results show that the wafer warpage predicted by FEM model demonstrates only about $10 \mu m$ maximum deviation over an $80 \mu m -$bowed wafer. An accurate stress model for an 8-inch wafer including full BiCMOS process is successfully developed and validated.