Stack memory implementation and analysis of timing constraint, power and memory using FPGA

Abstract

Stack memory is an approach in which information is entered and deleted from the memory segment in the pattern of last in the first out mechanism. In this work of analysis, the algorithm is implemented on a different type of FPGA platforms like Virtex-4, Virtex-5, Virtex-6, Virtex-6 low power and virtex7 low voltage where very detailed observations/investigations were made about timing constraint, memory utilization, and power dissipation. The main focus is to design and develop a system which is energy efficient. Therefore, VHDL programming is used to perform this investigation with the help of Xilinx ISE design suite which is synthesis tool. Basically, this software provides detailed information about various facets of a digital system that is important for the prior understanding of its real-time output, so that source used to realize the project should not be wasted and results to be the energy efficient design. Among these five type of FPGA, Virtex-4 and Virtex-7 low voltage were considered as the most energy efficient platforms. The developed system is energy efficient as the algorithm ensures less memory utilization, less power consumption and short time for signal travel.