A New Method for Synthesis of Self-Timed Combinational Circuits with Strong Indication

Abstract

Due to the clock signal's problems, in the design of synchronous circuits today, asynchronous circuits are a design alternative because they operate by event, so they do not use the clock signal. An essential class of asynchronous circuits, due to simplified timing analysis and robustness to PVT variations (process, supply voltage, temperature), is the class called quasi delay insensitive (QDI). However, QDI circuits have high overhead due to signal coding, which uses delay insensitive code and excessive C elements. This paper proposes a new architecture based on basic gates and laches RS to implement self-timed combinatorial circuits (ST _ CC). The ST _ CC circuits implemented in the new architecture interact with the environment in strong-indication; therefore, they are highly robust in interacting with the environment. The proposal proves to be promising for six benchmarks comparing the proposed architecture with miscellaneous architectures from the literature. Our proposal achieved an average reduction of up to 59.2 % in transistors without using C elements.