Reliability-Aware Scheduling on Heterogeneous Multicore Processors

Ajeya Naithani, Stijn Eyerman, L. Eeckhout
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引用次数: 24

Abstract

Reliability to soft errors is an increasingly important issue as technology continues to shrink. In this paper, we show that applications exhibit different reliability characteristics on big, high-performance cores versus small, power-efficient cores, and that there is significant opportunity to improve system reliability through reliability-aware scheduling on heterogeneous multicore processors. We monitor the reliability characteristics of all running applications, and dynamically schedule applications to the different core types in a heterogeneous multicore to maximize system reliability. Reliability-aware scheduling improves reliability by 25.4% on average (and up to 60.2%) compared to performance-optimized scheduling on a heterogeneous multicore processor with two big cores and two small cores, while de-grading performance by 6.3% only. We also introduce a novel system-level reliability metric for multiprogram workloads on (heterogeneous) multicores. We further show that our reliability-aware scheduler is robust across core count, number of big and small cores, and their frequency settings. The hardware cost in support of our reliability-aware scheduler is limited to 296 bytes per core.
异构多核处理器的可靠性感知调度
随着技术的不断萎缩,对软错误的可靠性问题变得越来越重要。在本文中,我们展示了应用程序在大型高性能核心上与小型节能核心上表现出不同的可靠性特征,并且通过在异构多核处理器上进行可靠性感知调度来提高系统可靠性有很大的机会。我们监控所有正在运行的应用程序的可靠性特征,并动态地将应用程序调度到异构多核中的不同核心类型,以最大限度地提高系统可靠性。与具有两个大核和两个小核的异构多核处理器上的性能优化调度相比,可靠性感知调度平均提高了25.4%(最高可达60.2%),而性能仅降低了6.3%。我们还为(异构)多核上的多程序工作负载引入了一种新的系统级可靠性度量。我们进一步表明,我们的可靠性感知调度器在核数、大核和小核的数量以及它们的频率设置上都是健壮的。支持我们的可靠性感知调度器的硬件成本被限制在每核296字节。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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