A pipelined, weakly ordered bus for multiprocessing systems

Abstract

With the PowerPC 620 microprocessor, we introduce a new bus optimized for server-class systems requiring significant multiprocessing capability. The 620 bus supports the 64-bit PowerPC Architecture specification with a 40-bit physical address bus and a separate 128-bit data bus. The address snoop response is pipelined with the address bus, providing an address transfer rate of up to 33M Addresses/sec at 66 MHz. Completion of address bus operations can be reordered with respect to operation initiation. The address and data buses are explicitly tagged allowing data transfers to be reordered with respect to the addresses. The data bus can transfer up to 1.0 GB/sec at 66 MHz. The bus protocol presented supports the snoop-based MESI cache coherency protocol and direct cache-to-cache data transfers.