DG-SOI ratioed logic with symmetric DG load - a novel approach for sub 50 nm LV/LP circuit design

Abstract

This paper investigates the possibility of using SDG (symmetric double gate) device intrinsically on structure as a load device for DG-SOI based ratioed logic, To establish the feasibility and superiority of this approach an inverter and a NOR gate were designed, which exhibits considerable advantages. The work is then extented to show how the approach can also be used to built NAND and XOR gates to create a complete logic family. All the simulations are done for 50 nm gate length devices using SILVACO tools. Voltage transfer characteristics are studied for both SDG load and ADG (asymmetric double gate) inverter. The transient characteristics obtained with a 1.25 GHz pulse on the n/sup +/-poly gate and a 500 MHz on the p/sup +/-poly gate are also studied.