An optimized isolated 5V EDMOS in 55nm LPx platform for use in Power Amplifier applications

Abstract

Power Amplifier (PA) modules are becoming more and more complex in modern wireless systems. In order to meet the efficiency/linearity design schemes such as Envelope elimination and restoration (EER) and Envelope tracking (ET) are increasingly becoming popular in PA applications. This paper describes an optimized isolated 5V EDMOS in 55nm Low Power extended (LPx) platform which is ideal for use in the bias modulator and controller of the PA module. Industry leading Rsp of 0.96 mohm-mm2 for high voltage NMOS and 2.6 mohm-mm2 for the high voltage PMOS is reported. Drain to source breakdown voltages of 10.5V was achieved for these devices. Due to special considerations given to optimizing the CGD capacitance while maintaining the Rsp, high Johnson's figure of merit (fT*BVDS) of 536 GHz-V and 168 GHz-V were achieved for the NMOS and PMOS respectively.