17.2 A 64kb 16nm asynchronous disturb current free 2-port SRAM with PMOS pass-gates for FinFET technologies

Abstract

FinFET technology has been adopted in the 16nm node because it provides superior lon/loff ratio, short-channel effect and local variation [1,2]. 2P-SRAM, which offers simultaneous read and write operations, is widely used for media processing because of its high operating efficiency. However, 2P-SRAM using the conventional 2P8T cell has a read-disturb issue, when both read wordline (RWL) and write word-line (WWL) are asserted simultaneously in the same row [3]. Furthermore, read-disturb becomes worse in FinFET technology compared with classical planar technology. In order to overcome these problems, we develop a disturb-current-free (DCF) 2P8T cell with PMOS write pass-gates and peripheral assist circuits to further improve its performance.