Robustness-Aware Design Space Exploration Through Iterative Refinement of D-Optimal Designs

Abstract

Design space exploration (DSE) is nowadays of utmost importance to implement HW designs with acceptable levels of performance, power consumption, area and dependability (PPAD). Electronic Design Automation (EDA) tools support the transformation of HW description models into technology-dependent implementations. Although designers can influence this process by tuning the parameters offered by EDA toolkits, determining their proper configuration is a complex and very time-consuming DSE problem rarely addressed from a PPAD perspective. On one hand, the spatial and temporal complexity of considered targets and the level of abstraction of their descriptions pose problems for the rapid execution of fault injection campaigns. On the other hand, the multi-level nature of parameters offered by EDA toolkits lead to an explosion of possible configurations to exercise during experimentation. This paper shows how to combine the D-optimal design of experiments with FPGA-based and statistical fault injection to significantly reduce not only the number of such configurations but also the number of faults to inject and the time required to perform each injection. All of this without compromising the statistical significance of results. The proposal is exemplified through the Xilinx Vivado Design Suite, which integrates one of the FPGA-based EDA toolkits most widely-used today in the industry, and the MC8051 IP core, a synthesizable microcontroller from Oregano Systems.