An Automated Static CMOS Schematic Generation Using MATLAB

Kapinesh G, Sachin Kumaran K, Sona Susan Jacob, Ragunath G
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Abstract

Nowadays, demands of integrated circuits (IC) increase day by day for many industries applications. The transistors count per IC also increases according to Moore’s law to speed up the process. The power consumption of IC is more due to huge transistors count. Digital circuits are one of a major part in ICs. There are varieties of method discussed to reduce the power consumption of digital circuits. Few are using less operating voltage, clock gating, multiple voltage levels and etc. In this paper we suggested to reduce the power consumption of digital circuits in IC by directly getting the equivalent CMOS circuits instead of standard cells. By this method, we can reduce the required transistors count for digital circuits design. We have written MATLAB program plotting static CMOS circuit directly for Boolean function, because none of the tool gives static CMOS circuit automatically.
基于MATLAB的静态CMOS原理图自动生成
如今,许多行业应用对集成电路的需求日益增加。根据摩尔定律,每个集成电路的晶体管数量也会增加,以加快这一过程。由于晶体管数量庞大,集成电路的功耗更高。数字电路是集成电路的主要组成部分之一。降低数字电路功耗的方法有多种。很少有人使用较少的工作电压,时钟门控,多电压电平等。在本文中,我们建议通过直接获得等效的CMOS电路而不是标准单元来降低IC中数字电路的功耗。通过这种方法,可以减少数字电路设计所需的晶体管数量。由于没有一种工具能自动给出静态CMOS电路,因此我们编写了MATLAB程序直接绘制布尔函数的静态CMOS电路。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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