Trends in the design of high-speed, low-power analog-to-digital converters

Abstract

This paper presents the design trends of high-resolution and high-speed Analog-to-Digital Converters (ADCs) which are employed in wireless LAN and ultra-wideband systems. The main research topic of such ADCs is reducing the power consumption. A number of reported low-power ADCs are classified into five types of ADCs. To understand the design challenges and the design techniques of low-power ADC, circuit configuration and basic operation of such five architectures are briefly reviewed. In addition, a guideline for architecture selection is discussed using a benchmark plot of recent developed ADCs. A future work of the ADC development also is discussed at the end of the paper.