{"title":"An Inverter-based On-chip Voltage Reference Generator for Low Power Application","authors":"Yuchen Zhao, Z. Zou, Lirong Zheng","doi":"10.1109/socc49529.2020.9524793","DOIUrl":null,"url":null,"abstract":"This paper presents an on-chip voltage reference generator for low power applications. The circuits consist of an array of inverters, a switch-capacitor, and a notch filter. The proposed circuits avoid using any bipolar junction transistor (BJT) and only contain MOSFETS and capacitors. The inverter is utilized as the core circuit to generate the reference voltage. The changes in temperature and process are suppressed by using the switch-capacitor. A notch filter is adopted for ripple reduction. This work is designed and simulated in a 0.18 µm CMOS process. Due to the mostly-digital architecture, this circuit can operate at a sub-1 V supply and generate a reference voltage of 0.504 V with a temperature coefficient of 20 ppm. The power consumption is 83 nW.","PeriodicalId":114740,"journal":{"name":"2020 IEEE 33rd International System-on-Chip Conference (SOCC)","volume":"409 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2020-09-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 IEEE 33rd International System-on-Chip Conference (SOCC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/socc49529.2020.9524793","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
This paper presents an on-chip voltage reference generator for low power applications. The circuits consist of an array of inverters, a switch-capacitor, and a notch filter. The proposed circuits avoid using any bipolar junction transistor (BJT) and only contain MOSFETS and capacitors. The inverter is utilized as the core circuit to generate the reference voltage. The changes in temperature and process are suppressed by using the switch-capacitor. A notch filter is adopted for ripple reduction. This work is designed and simulated in a 0.18 µm CMOS process. Due to the mostly-digital architecture, this circuit can operate at a sub-1 V supply and generate a reference voltage of 0.504 V with a temperature coefficient of 20 ppm. The power consumption is 83 nW.