Time-Domain Multiply-Accumulator using Digital-to-Time Multiplier for CNN Processors in 28-nm CMOS

Abstract

This paper proposes a time-domain multiply-accumulator (MAC) circuit exploiting the use of a digital-to-time multiplier (DTM) unit for performing convolutional operations and designed in 28nm CMOS. As the foundational calculation of state-of-the-art convolutional neural network (CNN) models, convolutional operation could normally be executed millions of times in one CNN task. The proposed circuit is designed to support this large computational resource requirement during the CNN computations. It is running in time-domain with 6-bit resolution (1 sign bit) and performs calculations based on corresponding time delays. Compared with other analog-domain propositions, time-domain designs perform better, with higher operating frequencies up to 50 MHz. In schematic simulations, the proposed DTM unit, operating with 5 bits, achieves 0.1 GOPS ideal throughput and consumes 74.79 µW at 1.0V supply.