DTCO and TCAD for a 12 Layer-EUV Ultra-Scaled Surrounding Gate Transistor 6T-SRAM

Abstract

A flow, module steps and key structural elements enabling a surrounding gate transistor (SGT) based 6T-SRAM with 50nm pillar pitch and 0.0205 um2 are presented, with emphasis on process challenges and innovations. A new DTCO/TCAD methodology is used to explore the design space, demonstrate the bit cell functionality and optimize the process. In particular, it is shown that vertical SGT are extremely sensitive to gate misalignment and that buried bottom contact makes the process immune to doping variations and misalignments.