Layout-level design for testability rules for a CMOS cell library

M. Rullán, F. C. Blom, J. Oliver, C. Ferrer
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引用次数: 1

Abstract

In CMOS technology there are some faults (opens and shorts) that are hard to detect or even undetectable. For this reason layout level design for testability (LLDFT) rules have been developed. These rules prevent the faults or reduce the appearance probability of them. The purpose of this work is to apply a practical set of LLDFT rules on the cells of the library designed at the Centre Nacional de Microelectronica (CNM) in order to obtain a highly testable cell library. The authors summarize the main results (area overhead and performance degradation) of the application of the LLDFT rules on the cells.<>
CMOS单元库可测试性规则的布局级设计
在CMOS技术中存在一些难以检测甚至无法检测的故障(开路和短路)。基于这个原因,可测试性布局关卡设计(LLDFT)规则被开发出来。这些规则可以防止故障或降低故障出现的概率。这项工作的目的是在国家微电子中心(CNM)设计的细胞库中应用一套实用的LLDFT规则,以获得一个高度可测试的细胞库。作者总结了在单元上应用LLDFT规则的主要结果(面积开销和性能下降)
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