Optimising ring oscillator frequency on a novel FPGA device via partial reconfiguration

Abstract

The random variations which are present at submicron technology nodes have been proven to have significant impact on both yield and device performance. The circuit-scale effects of transistor variability for a particular architecture are hard to estimate, and device manufacturers face the risk of functional failures due to these stochastic variations, which is a growing problem for the FPGA community and the circuit design community in general. The novel PAnDA architecture aims to tackle some of those effects by allowing post-fabrication reconfiguration of the fabric, which in turn makes it possible to both optimise performance of a singular chip and to reduce the impact that these adverse effects have on manufacturing yield. A series of 3 stage ring oscillator circuits are mapped onto the PAnDA fabric, and a Genetic Algorithm is used to find a configuration which minimises the difference in frequency between the oscillator outputs and a target. Combinations of transistor sizes are used to induce changes in the performance of the logic blocks. A configuration is found which reduces the difference in frequencies to less than 1.5%.