Logic Circuit Implementation for Enabling SRAM Based In Memory Computing

Abstract

Von-Neumann architecture which physically decouples the storage/memory and processing blocks suffers from well-known memory bottleneck. In-memory computing (IMC) is a promising architecture to cope up with this bottleneck, where memory performs the computation along with its usual storage function. This paper presents the implementation of the half adder and half-subtractor circuits using the 6T SRAM architecture. The circuits require minimal peripheral changes. It also proposes the implementation of 2×1 multiplexer using the concept of copy operation within SRAM cells without using much peripheral circuitries. The simulation results confirm the logic functionality for all the possible cases. Since our proposals maintain the 6T-SRAM architecture with minimal peripherals, it can be used as a memory unit with usual read-write operation and also as an on-demand basic computing unit.