Adaptive page allocation of DRAM/PCRAM hybrid memory architecture

Abstract

In this paper, we propose an adaptive page allocation and buffer management methodology for the hierarchical DRAM/PCRAM memory architecture. A small DRAM is used as cache of PCRAM memory to reduce leakage power consumption, and an adaptive page allocation scheme is used to make better utilization of the small DRAM capacity, such that conflict misses of DRAM are minimized under the multi-core architecture. Therefore, the number of write back to PCRAM and data migration between PCRAM and DRAM is obviously reduced. Experimental results show that our methodology is effective in improving both the energy consumption and access latency of PCRAM by 25%.