Mapping physical defects to logic level for defect oriented testing

R. Ubar
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引用次数: 1

Abstract

A uniform fault model for representing physical defects in components of digital circuits is introduced. Physical defects are modeled as parameters in generic Boolean differential equations. Solutions of the equations give the conditions at which defects are locally activated. The defect activation conditions are used as functional fault models on the logic level for fault simulation purposes. The functional fault model can be regarded also as an interface for mapping faults from one system level to another, helping to carry out hierarchical test generation or hierarchical fault simulation in digital systems. Experiments have shown the feasibility and efficiency of the method compared to the classical stuck-at fault based approaches.
为面向缺陷的测试,将物理缺陷映射到逻辑级别
介绍了一种用于表示数字电路元件物理缺陷的统一故障模型。物理缺陷被建模为一般布尔微分方程中的参数。方程的解给出了缺陷局部激活的条件。将缺陷激活条件作为逻辑层的功能故障模型,用于故障仿真。功能故障模型也可以看作是将故障从一个系统级别映射到另一个系统级别的接口,有助于在数字系统中进行分层测试生成或分层故障仿真。实验结果表明,与传统的基于故障卡滞的方法相比,该方法具有较好的可行性和有效性。
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