A Novel BIST TPG for Testing of VLSI Circuits

Abstract

Design for low power testing is primary concern in modern VLSI circuits. In this paper a novel test pattern generator (TPG) is proposed which is more suitable for built in self test (BIST) architecture, used for testing of VLSI circuits. The objective of the BIST is to reduce power consumption during testing of VLSI circuits. In CMOS devices 80% of power consumption is due to switching activity occurred during operation. The proposed TPG is based on read only memory (ROM) which is carefully designed to store the test vectors with minimum area over the conventional ROM. This reduces the number of CMOS transistors significantly when compared to that of LFSR/counter TPG. The proposed TPG is more suitable for deterministic pattern testing and the fault coverage is improved over the LFSR. Low power reordered test patterns also can also be stored in the same order to reduce the test power in circuit under test (CUT). The TPG is designed and implemented for benchmark circuits ISCAS 85 and 89. Experimental results shows that a considerable reduction in number of CMOS devices and test power is achieved over the LFSR-TPG