{"title":"Dual stage analog cancellation of linear and nonlinear self interference for full duplex radio","authors":"S. Narieda","doi":"10.1109/PIMRC.2015.7343350","DOIUrl":null,"url":null,"abstract":"This paper presents dual stage analog cancellation architectures of a linear and nonlinear self interference signal. The presented architecture has two cancelers which are placed at an RF and baseband stage on an analog domain. The replica signal for the analog baseband canceler is regenerated in a digital domain, and the signal outputs a DAC. The purpose of the presented architecture is to mitigate the effect of the AGC and ADC on the receiver performance. Numerical examples are provided to validate the effectiveness of the presented technique. From these results, it can be seen that 1) the performance of the presented can improve by increasing the bit resolution at the DAC, 2) the presented architecture can improve the bit resolution at the ADC.","PeriodicalId":274734,"journal":{"name":"2015 IEEE 26th Annual International Symposium on Personal, Indoor, and Mobile Radio Communications (PIMRC)","volume":"100 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-12-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 IEEE 26th Annual International Symposium on Personal, Indoor, and Mobile Radio Communications (PIMRC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/PIMRC.2015.7343350","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
This paper presents dual stage analog cancellation architectures of a linear and nonlinear self interference signal. The presented architecture has two cancelers which are placed at an RF and baseband stage on an analog domain. The replica signal for the analog baseband canceler is regenerated in a digital domain, and the signal outputs a DAC. The purpose of the presented architecture is to mitigate the effect of the AGC and ADC on the receiver performance. Numerical examples are provided to validate the effectiveness of the presented technique. From these results, it can be seen that 1) the performance of the presented can improve by increasing the bit resolution at the DAC, 2) the presented architecture can improve the bit resolution at the ADC.