Uniform SystemC Co-Simulation Methodology for System-on-Chip Designs

Abstract

The increasing complexity of the current and future system-on-chip designs poses enormous challenges to system-level design. The uniform SystemC co-simulation methodology is proposed to describe the whole chip entirely with the same language. Elimination of the interaction between different simulators brings significant speedup in co-simulation. The processor model divides every instruction into a number of atomic operations, which makes it possible to accomplish fully cycle-accurate simulation. Meanwhile, the transaction-level-modeling communication model enables each hardware block to be built at different abstraction levels. The methodology is demonstrated by the exemplary design of a MP3 decoding system.