Configurable CNN SoC Co-Processor Architecture

Abstract

In this paper we proposed a configurable CNN architecture design for use in a SoC co-processor. The co-processor is configured and generated by the proposed design tools utilizing folding architecture and multiple processing elements working in parallel. The proposed system utilized a configurable system designer that can automatically generate the verilog source file that defines a CNN processor that can process various image and kernel sizes. The system designer also able to generate the program code to be run on the SoC platform. The system design has been verified using a ZYNQTM 7000 SoC platform and shows the processing result is similar to the simulation results. The system can reach the processing speed of 72.727 MHz.