Efficient use of multipliers in microprocessor implementation of Hamming distance for binary sequence correlation

Abstract

The paper focuses on a microprocessor implementation of the Hamming distance for binary correlation. It uses the fact that the binary correlation result can be derived from binary convolution (i.e., modeled with AND gates instead of XOR); as a result, convolution of multiple bits with multiple bits can be computed by a single multiplication instruction. This follows from a general proof for base-n convolution that is presented. Furthermore, using a hierarchical shift-addition approach, we can also reduce the number of additions in the subsequent step. The paper also shows that this approach can also be used in the frequency domain where an N/spl times/N point binary circular convolution can be modeled using an N/spl times/M double precision FFT, where M is a sub-multiple of N depending on the kernel size. Comparison of the time/frequency approaches is presented for different kernel/image sizes, with the help of benchmarking results.